hollywood.h

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/*
        libbroadway - A general purpose library to control the Wii.
        Hollywood register definitions

Copyright (C) 2008, 2009        Haxx Enterprises <bushing@gmail.com>
Copyright (C) 2008, 2009        Sven Peter <svenpeter@gmail.com>
Copyright (C) 2008, 2009        Hector Martin "marcan" <marcan@marcansoft.com>
Copyright (C) 2008, 2009        John Kelley <wiidev@kelley.ca>
Copyright (C) 2009-2011         Alex Marshall <trap15@raidenii.net>

# This code is licensed to you under the terms of the GNU GPL, version 2;
# see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
*/

#ifndef __HOLLYWOOD_H__
#define __HOLLYWOOD_H__

/* Hollywood Registers */

#define         HW_GC_REG_BASE                  0xC000000                       
#define         HW_PPC_REG_BASE                 0xD000000                       
#define         HW_REG_BASE                     0xD800000                       
// The PPC can only see the first three IPC registers
#define         HW_IPC_PPCMSG                   (HW_REG_BASE + 0x000)           
#define         HW_IPC_PPCCTRL                  (HW_REG_BASE + 0x004)           
#define         HW_IPC_ARMMSG                   (HW_REG_BASE + 0x008)           
#define         HW_IPC_ARMCTRL                  (HW_REG_BASE + 0x00C)           
#define         HW_TIMER                        (HW_REG_BASE + 0x010)           
#define         HW_ALARM                        (HW_REG_BASE + 0x014)           
#define         HW_PPCIRQFLAG                   (HW_REG_BASE + 0x030)           
#define         HW_PPCIRQMASK                   (HW_REG_BASE + 0x034)           
#define         HW_ARMIRQFLAG                   (HW_REG_BASE + 0x038)           
#define         HW_ARMIRQMASK                   (HW_REG_BASE + 0x03C)           
#define         HW_MEMMIRR                      (HW_REG_BASE + 0x060)           
// something to do with PPCBOOT
// and legacy DI it seems ?!?
#define         HW_EXICTRL                      (HW_REG_BASE + 0x070)           
#define         EXICTRL_ENABLE_EXI              1                               
// PPC side of GPIO1 (Starlet can access this too)
// Output state
#define         HW_GPIO1B_OUT                   (HW_REG_BASE + 0x0C0)           
// Direction (1=output)
#define         HW_GPIO1B_DIR                   (HW_REG_BASE + 0x0C4)           
// Input state
#define         HW_GPIO1B_IN                    (HW_REG_BASE + 0x0C8)           
// Interrupt level
#define         HW_GPIO1B_INTLVL                (HW_REG_BASE + 0x0CC)           
// Interrupt flags (write 1 to clear)
#define         HW_GPIO1B_INTFLAG               (HW_REG_BASE + 0x0D0)           
// Interrupt propagation enable
// Do these interrupts go anywhere???
#define         HW_GPIO1B_INTENABLE             (HW_REG_BASE + 0x0D4)           
//??? seems to be a mirror of inputs at some point... power-up state?
#define         HW_GPIO1B_INMIR                 (HW_REG_BASE + 0x0D8)           
// 0xFFFFFF by default, if cleared disables respective outputs. Top bits non-settable.
#define         HW_GPIO1_ENABLE                 (HW_REG_BASE + 0x0DC)           
#define         HW_GPIO1_SLOT                   0x000020                        
#define         HW_GPIO1_DEBUG                  0xFF0000
#define         HW_GPIO1_DEBUG_SH               16

// Starlet side of GPIO1
// Output state
#define         HW_GPIO1_OUT                    (HW_REG_BASE + 0x0E0)           
// Direction (1=output)
#define         HW_GPIO1_DIR                    (HW_REG_BASE + 0x0E4)           
// Input state
#define         HW_GPIO1_IN                     (HW_REG_BASE + 0x0E8)           
// Interrupt level
#define         HW_GPIO1_INTLVL                 (HW_REG_BASE + 0x0EC)           
// Interrupt flags (write 1 to clear)
#define         HW_GPIO1_INTFLAG                (HW_REG_BASE + 0x0F0)           
// Interrupt propagation enable (interrupts go to main interrupt 0x800)
#define         HW_GPIO1_INTENABLE              (HW_REG_BASE + 0x0F4)           
//??? seems to be a mirror of inputs at some point... power-up state?
#define         HW_GPIO1_INMIR                  (HW_REG_BASE + 0x0F8)           
// Owner of each GPIO bit. If 1, GPIO1B registers assume control. If 0, GPIO1 registers assume control.
#define         HW_GPIO1_OWNER                  (HW_REG_BASE + 0x0FC)           
// ????
#define         HW_DIFLAGS                      (HW_REG_BASE + 0x180)           
#define         DIFLAGS_BOOT_CODE               0x100000

// maybe a GPIO???
#define         HW_RESETS                       (HW_REG_BASE + 0x194)           
#define         HW_CLOCKS                       (HW_REG_BASE + 0x1B4)           
#define         HW_GPIO2_OUT                    (HW_REG_BASE + 0x1C8)
#define         HW_GPIO2_DIR                    (HW_REG_BASE + 0x1CC)
#define         HW_GPIO2_IN                     (HW_REG_BASE + 0x1D0)

#define         HW_OTP_CMD                      (HW_REG_BASE + 0x1EC)           
#define         HW_OTP_DATA                     (HW_REG_BASE + 0x1F0)           
#define         HW_VERSION                      (HW_REG_BASE + 0x214)           
/* SI Registers */

#define         SI_REG_BASE                     (HW_PPC_REG_BASE + 0x06400)     
#define         SI_OUTBUF(x)                    (SI_REG_BASE + ((x) * 0xC))     
#define         SI_OUTBUF_0                     SI_OUTBUF(0)
#define         SI_OUTBUF_1                     SI_OUTBUF(1)
#define         SI_OUTBUF_2                     SI_OUTBUF(2)
#define         SI_OUTBUF_3                     SI_OUTBUF(3)
#define         SI_INBUFA(x)                    (SI_REG_BASE + 0x4 + ((x) * 0xC))       
#define         SI_INBUFA_0                     SI_INBUFA(0)
#define         SI_INBUFA_1                     SI_INBUFA(1)
#define         SI_INBUFA_2                     SI_INBUFA(2)
#define         SI_INBUFA_3                     SI_INBUFA(3)
#define         SI_INBUFB(x)                    (SI_REG_BASE + 0x8 + ((x) * 0xC))       
#define         SI_INBUFB_0                     SI_INBUFB(0)
#define         SI_INBUFB_1                     SI_INBUFB(1)
#define         SI_INBUFB_2                     SI_INBUFB(2)
#define         SI_INBUFB_3                     SI_INBUFB(3)
#define         SI_POLL                         (SI_REG_BASE + 0x30)            
#define         SI_CONTROL                      (SI_REG_BASE + 0x34)            
#define         SI_STATUS                       (SI_REG_BASE + 0x38)            
#define         SI_EXI_LOCK                     (SI_REG_BASE + 0x3C)            
#define         SI_IO_BUF                       (SI_REG_BASE + 0x80)            
/* NAND Registers */

#define         NAND_REG_BASE                   (HW_PPC_REG_BASE + 0x10000)     
#define         NAND_CMD                        (NAND_REG_BASE + 0x000)         
#define         NAND_STATUS                     NAND_CMD                        
#define         NAND_CONF                       (NAND_REG_BASE + 0x004)         
#define         NAND_ADDR0                      (NAND_REG_BASE + 0x008)         
#define         NAND_ADDR1                      (NAND_REG_BASE + 0x00C)         
#define         NAND_DATA                       (NAND_REG_BASE + 0x010)         
#define         NAND_ECC                        (NAND_REG_BASE + 0x014)         
#define         NAND_UNK1                       (NAND_REG_BASE + 0x018)
#define         NAND_UNK2                       (NAND_REG_BASE + 0x01C)

/* AES Registers */

#define         AES_REG_BASE                    (HW_PPC_REG_BASE + 0x20000)     
#define         AES_CMD                         (AES_REG_BASE + 0x000)          
#define         AES_SRC                         (AES_REG_BASE + 0x004)          
#define         AES_DEST                        (AES_REG_BASE + 0x008)          
#define         AES_KEY                         (AES_REG_BASE + 0x00C)          
#define         AES_IV                          (AES_REG_BASE + 0x010)          
/* SHA-1 Registers */

#define         SHA_REG_BASE                    (HW_PPC_REG_BASE + 0x30000)     
#define         SHA_CMD                         (SHA_REG_BASE + 0x000)          
#define         SHA_SRC                         (SHA_REG_BASE + 0x004)          
#define         SHA_H0                          (SHA_REG_BASE + 0x008)          
#define         SHA_H1                          (SHA_REG_BASE + 0x00C)          
#define         SHA_H2                          (SHA_REG_BASE + 0x010)          
#define         SHA_H3                          (SHA_REG_BASE + 0x014)          
#define         SHA_H4                          (SHA_REG_BASE + 0x018)          
/* EHCI Registers */
#define         EHCI_REG_BASE                   (HW_PPC_REG_BASE + 0x40000)     
/* stolen from mikep2 patched linux kernel: drivers/usb/host/ohci-mipc.c */
#define         EHCI_CTL                        (EHCI_REG_BASE + 0xCC)
/* oh0 interrupt enable */
#define         EHCI_CTL_OH0INTE                (1 << 11)
/* oh1 interrupt enable */
#define         EHCI_CTL_OH1INTE                (1 << 12)

/* OHCI0 Registers */
#define         OHCI0_REG_BASE                  (HW_PPC_REG_BASE + 0x50000)     
/* OHCI1 Registers */
#define         OHCI1_REG_BASE                  (HW_PPC_REG_BASE + 0x60000)     
#define         OHCI_HC_REVISION                0x00
#define         OHCI_HC_CONTROL                 0x04
#define         OHCI_HC_COMMAND_STATUS          0x08
#define         OHCI_HC_INT_STATUS              0x0C

#define         OHCI_HC_INT_ENABLE              0x10
#define         OHCI_HC_INT_DISABLE             0x14
#define         OHCI_HC_HCCA                    0x18
#define         OHCI_HC_PERIOD_CURRENT_ED       0x1C

#define         OHCI_HC_CTRL_HEAD_ED            0x20
#define         OHCI_HC_CTRL_CURRENT_ED         0x24
#define         OHCI_HC_BULK_HEAD_ED            0x28
#define         OHCI_HC_BULK_CURRENT_ED         0x2C

#define         OHCI_HC_DONE_HEAD               0x30
#define         OHCI_HC_FM_INTERVAL             0x34
#define         OHCI_HC_FM_REMAINING            0x38
#define         OHCI_HC_FM_NUMBER               0x3C

#define         OHCI_HC_PERIODIC_START          0x40
#define         OHCI_HC_LS_THRESHOLD            0x44
#define         OHCI_HC_RH_DESCRIPTOR_A         0x48
#define         OHCI_HC_RH_DESCRIPTOR_B         0x4C

#define         OHCI_HC_RH_STATUS               0x50
#define         OHCI_HC_RH_PORT_STATUS_1        0x54
#define         OHCI_HC_RH_PORT_STATUS_2        0x58


/* SD Host Controller Registers */
#define         SDHC_REG_BASE                   (HW_PPC_REG_BASE + 0x70000)     
/* Drive Interface registers */
#define         DI_REG_BASE                     (HW_REG_BASE + 0x06000)         
#define         DI_STATUS                       (DI_REG_BASE + 0x00)            
#define         DI_COVER                        (DI_REG_BASE + 0x04)            
#define         DI_COMMAND                      (DI_REG_BASE + 0x08)            
#define         DI_CMD_OFFSET                   (DI_REG_BASE + 0x0C)            
#define         DI_CMD_LEN                      (DI_REG_BASE + 0x10)            
#define         DI_DMA_ADDR                     (DI_REG_BASE + 0x14)            
#define         DI_DMA_LEN                      (DI_REG_BASE + 0x18)            
#define         DI_CONTROL                      (DI_REG_BASE + 0x1C)            
#define         DI_IMM_BUF                      (DI_REG_BASE + 0x20)            
#define         DI_CONFIG                       (DI_REG_BASE + 0x24)            
/* EXI Registers */
#define         EXI_REG_BASE                    (HW_REG_BASE + 0x06800)         
#define         EXI_BOOT_BASE                   (EXI_REG_BASE + 0x040)          
#define         EXI_CSR(x)                      (EXI_REG_BASE + (0x14 * (x)) + 0x00)    
#define         EXI_MAR(x)                      (EXI_REG_BASE + (0x14 * (x)) + 0x04)    
#define         EXI_LENGTH(x)                   (EXI_REG_BASE + (0x14 * (x)) + 0x08)    
#define         EXI_CR(x)                       (EXI_REG_BASE + (0x14 * (x)) + 0x0C)    
#define         EXI_DATA(x)                     (EXI_REG_BASE + (0x14 * (x)) + 0x10)    
/* EXI0 Registers */
#define         EXI0_REG_BASE                   EXI_CSR(0)                      
#define         EXI0_CSR                        EXI_CSR(0)
#define         EXI0_MAR                        EXI_MAR(0)
#define         EXI0_LENGTH                     EXI_LENGTH(0)
#define         EXI0_CR                         EXI_CR(0)
#define         EXI0_DATA                       EXI_DATA(0)

/* EXI1 Registers */
#define         EXI1_REG_BASE                   EXI_CSR(1)                      
#define         EXI1_CSR                        EXI_CSR(1)
#define         EXI1_MAR                        EXI_MAR(1)
#define         EXI1_LENGTH                     EXI_LENGTH(1)
#define         EXI1_CR                         EXI_CR(1)
#define         EXI1_DATA                       EXI_DATA(1)

/* EXIT2 Registers */
#define         EXI2_REG_BASE                   EXI_CSR(2)                      
#define         EXI2_CSR                        EXI_CSR(2)
#define         EXI2_MAR                        EXI_MAR(2)
#define         EXI2_LENGTH                     EXI_LENGTH(2)
#define         EXI2_CR                         EXI_CR(2)
#define         EXI2_DATA                       EXI_DATA(2)


/* Audio Interface registers */
#define         AI_REG_BASE                     (HW_REG_BASE + 0x06C00)         
#define         AI_CONTROL                      (AI_REG_BASE + 0x00)            
#define         AI_VOLUME                       (AI_REG_BASE + 0x04)            
#define         AI_AISCNT                       (AI_REG_BASE + 0x08)            
#define         AI_AIIT                         (AI_REG_BASE + 0x0C)            
/* MEMORY CONTROLLER Registers */
#define         MEM_REG_BASE                    (HW_REG_BASE + 0xB4000)         
#define         MEM_PROT                        (MEM_REG_BASE + 0x20A)          
#define         MEM_PROT_START                  (MEM_REG_BASE + 0x20C)          
#define         MEM_PROT_END                    (MEM_REG_BASE + 0x20E)          
#define         MEM_FLUSHREQ                    (MEM_REG_BASE + 0x228)          
#define         MEM_FLUSHACK                    (MEM_REG_BASE + 0x22A)          
#define         GX32BIT(x)                      ({ typeof(x) _x = (x); \
                                                 ((_x & 0xFFFF0000) >> 16) | \
                                                 ((_x & 0x0000FFFF) << 16); })

/* Command Processor registers */
#define         CP_REG_BASE                     (HW_GC_REG_BASE + 0x00000)      
#define         CP_STATUS                       (CP_REG_BASE + 0x00)            
#define         CP_CONTROL                      (CP_REG_BASE + 0x02)            
#define         CP_CLEAR                        (CP_REG_BASE + 0x04)            
#define         CP_TOKEN                        (CP_REG_BASE + 0x0E)            
#define         CP_BOUNDING_BOX_L               (CP_REG_BASE + 0x10)            
#define         CP_BOUNDING_BOX_R               (CP_REG_BASE + 0x12)            
#define         CP_BOUNDING_BOX_T               (CP_REG_BASE + 0x14)            
#define         CP_BOUNDING_BOX_B               (CP_REG_BASE + 0x16)            
#define         CP_PIPE_BASE                    (CP_REG_BASE + 0x20)            
#define         CP_PIPE_END                     (CP_REG_BASE + 0x24)            
#define         CP_PIPE_HI_WATERMARK            (CP_REG_BASE + 0x28)            
#define         CP_PIPE_LO_WATERMARK            (CP_REG_BASE + 0x2C)            
#define         CP_PIPE_DISTANCE                (CP_REG_BASE + 0x30)            
#define         CP_PIPE_WRITE_PTR               (CP_REG_BASE + 0x34)            
#define         CP_PIPE_READ_PTR                (CP_REG_BASE + 0x38)            
#define         CP_PIPE_BP                      (CP_REG_BASE + 0x3C)            
/* Pixel Engine registers */
#define         PE_REG_BASE                     (HW_GC_REG_BASE + 0x01000)      
#define         PE_Z_CONFIG                     (PE_REG_BASE + 0x00)            
#define         PE_ALPHA_CONFIG                 (PE_REG_BASE + 0x02)            
#define         PE_DEST_ALPHA                   (PE_REG_BASE + 0x04)            
#define         PE_ALPHA_MODE                   (PE_REG_BASE + 0x06)            
#define         PE_ALPHA_READ                   (PE_REG_BASE + 0x08)            
#define         PE_IRQ_FLAG                     (PE_REG_BASE + 0x0A)            
#define         PE_TOKEN                        (PE_REG_BASE + 0x0E)            
/* Video Interface registers */
#define         VI_REG_BASE                     (HW_GC_REG_BASE + 0x02000)      
#define         VI_VTIMING                      (VI_REG_BASE + 0x00)            
#define         VI_STATUS                       (VI_REG_BASE + 0x02)            
#define         VI_HTIMING0                     (VI_REG_BASE + 0x04)            
#define         VI_HTIMING1                     (VI_REG_BASE + 0x08)            
#define         VI_ODD_VTIMING                  (VI_REG_BASE + 0x0C)            
#define         VI_EVEN_VTIMING                 (VI_REG_BASE + 0x10)            
#define         VI_ODD_BBLANK_INTRVL            (VI_REG_BASE + 0x14)            
#define         VI_EVEN_BBLANK_INTRVL           (VI_REG_BASE + 0x18)            
#define         VI_FRAMEBUFFER_0                (VI_REG_BASE + 0x1C)            
#define         VI_FRAMEBUFFER_0_R              (VI_REG_BASE + 0x20)            
#define         VI_FRAMEBUFFER_1                (VI_REG_BASE + 0x24)            
#define         VI_FRAMEBUFFER_1_R              (VI_REG_BASE + 0x28)            
#define         VI_VPOS                         (VI_REG_BASE + 0x2C)            
#define         VI_HPOS                         (VI_REG_BASE + 0x2E)            
#define         VI_DISP_IRQ0                    (VI_REG_BASE + 0x30)            
#define         VI_DISP_IRQ1                    (VI_REG_BASE + 0x34)            
#define         VI_DISP_IRQ2                    (VI_REG_BASE + 0x38)            
#define         VI_DISP_IRQ3                    (VI_REG_BASE + 0x3C)            
#define         VI_DISP_LATCH0                  (VI_REG_BASE + 0x40)            
#define         VI_DISP_LATCH1                  (VI_REG_BASE + 0x44)            
#define         VI_HSCALE_WIDTH                 (VI_REG_BASE + 0x48)            
#define         VI_HSCALE_STEP                  (VI_REG_BASE + 0x4A)            
#define         VI_FILTER_COEFF0                (VI_REG_BASE + 0x4C)            
#define         VI_FILTER_COEFF1                (VI_REG_BASE + 0x50)            
#define         VI_FILTER_COEFF2                (VI_REG_BASE + 0x54)            
#define         VI_FILTER_COEFF3                (VI_REG_BASE + 0x58)            
#define         VI_FILTER_COEFF4                (VI_REG_BASE + 0x5C)            
#define         VI_FILTER_COEFF5                (VI_REG_BASE + 0x60)            
#define         VI_FILTER_COEFF6                (VI_REG_BASE + 0x64)            
#define         VI_CLOCK                        (VI_REG_BASE + 0x6C)            
#define         VI_DTV_STATUS                   (VI_REG_BASE + 0x6E)            
#define         VI_UNKNOWN                      (VI_REG_BASE + 0x70)
#define         VI_BORDER_HBLANK_END            (VI_REG_BASE + 0x72)            
#define         VI_BORDER_HBLANK_START          (VI_REG_BASE + 0x74)            
/* Processor Interface registers */
#define         PI_REG_BASE                     (HW_GC_REG_BASE + 0x03000)      
#define         PI_INT_CAUSE                    (PI_REG_BASE + 0x00)            
#define         PI_INT_MASK                     (PI_REG_BASE + 0x04)            
#define         PI_PIPE_START                   (PI_REG_BASE + 0x0C)            
#define         PI_PIPE_END                     (PI_REG_BASE + 0x10)            
#define         PI_PIPE_WRITE_PTR               (PI_REG_BASE + 0x14)            
#define         PI_RESET                        (PI_REG_BASE + 0x24)            
#define         PI_CONSOLE_TYPE                 (PI_REG_BASE + 0x2C)            
/* Memory Interface registers */
#define         MI_REG_BASE                     (HW_GC_REG_BASE + 0x04000)      
#define         MI_PROT_RGNTOP(x)               (MI_REG_BASE + (4 * (x)))       
#define         MI_PROT_RGNBOT(x)               (MI_REG_BASE + (4 * (x)) + 2)   
#define         MI_PROT_RGN0T                   MI_PROT_RGNTOP(0)               
#define         MI_PROT_RGN1T                   MI_PROT_RGNTOP(1)               
#define         MI_PROT_RGN2T                   MI_PROT_RGNTOP(2)               
#define         MI_PROT_RGN3T                   MI_PROT_RGNTOP(3)               
#define         MI_PROT_RGN0B                   MI_PROT_RGNBOT(0)               
#define         MI_PROT_RGN1B                   MI_PROT_RGNBOT(1)               
#define         MI_PROT_RGN2B                   MI_PROT_RGNBOT(2)               
#define         MI_PROT_RGN3B                   MI_PROT_RGNBOT(3)               
#define         MI_PROT_TYPE                    (MI_REG_BASE + 0x10)            
#define         MI_IRQMASK                      (MI_REG_BASE + 0x1C)            
#define         MI_IRQFLAG                      (MI_REG_BASE + 0x1E)            
/* Don't know what this does */
/* Clear it in IRQ please */
#define         MI_UNKNOWN1                     (MI_REG_BASE + 0x20)

/* Address protection exception occurred on */
#define         MI_PROT_ADDRLO                  (MI_REG_BASE + 0x22)            
#define         MI_PROT_ADDRHI                  (MI_REG_BASE + 0x24)            
/* What are these timers? */
/* Writing anything clears them */
#define         MI_PROT_TIMER0H                 (MI_REG_BASE + 0x32)            
#define         MI_PROT_TIMER0L                 (MI_REG_BASE + 0x34)            
#define         MI_PROT_TIMER1H                 (MI_REG_BASE + 0x36)            
#define         MI_PROT_TIMER1L                 (MI_REG_BASE + 0x38)            
#define         MI_PROT_TIMER2H                 (MI_REG_BASE + 0x3A)            
#define         MI_PROT_TIMER2L                 (MI_REG_BASE + 0x3C)            
#define         MI_PROT_TIMER3H                 (MI_REG_BASE + 0x3E)            
#define         MI_PROT_TIMER3L                 (MI_REG_BASE + 0x40)            
#define         MI_PROT_TIMER4H                 (MI_REG_BASE + 0x42)            
#define         MI_PROT_TIMER4L                 (MI_REG_BASE + 0x44)            
#define         MI_PROT_TIMER5H                 (MI_REG_BASE + 0x46)            
#define         MI_PROT_TIMER5L                 (MI_REG_BASE + 0x48)            
#define         MI_PROT_TIMER6H                 (MI_REG_BASE + 0x4A)            
#define         MI_PROT_TIMER6L                 (MI_REG_BASE + 0x4C)            
#define         MI_PROT_TIMER7H                 (MI_REG_BASE + 0x4E)            
#define         MI_PROT_TIMER7L                 (MI_REG_BASE + 0x50)            
#define         MI_PROT_TIMER8H                 (MI_REG_BASE + 0x52)            
#define         MI_PROT_TIMER8L                 (MI_REG_BASE + 0x54)            
#define         MI_PROT_TIMER9H                 (MI_REG_BASE + 0x56)            
#define         MI_PROT_TIMER9L                 (MI_REG_BASE + 0x58)            
/* Judging by this being with the timers, possibly a timer controller? */
#define         MI_UNKNOWN2                     (MI_REG_BASE + 0x5A)            
/* DSP registers */
#define         DSP_REG_BASE                    (HW_GC_REG_BASE + 0x05000)      
#define         DSP_MAILBOX_IN_H                (DSP_REG_BASE + 0x00)           
#define         DSP_MAILBOX_IN_L                (DSP_REG_BASE + 0x02)           
#define         DSP_MAILBOX_OUT_H               (DSP_REG_BASE + 0x04)           
#define         DSP_MAILBOX_OUT_L               (DSP_REG_BASE + 0x06)           
#define         DSP_STATUS                      (DSP_REG_BASE + 0x0A)           
#define         DSP_IRQ_CTRL                    (DSP_REG_BASE + 0x10)           
/* DSP ARAM interface */
#define         DSP_ARAM_SIZE                   (DSP_REG_BASE + 0x12)           
#define         DSP_ARAM_MODE                   (DSP_REG_BASE + 0x16)           
#define         DSP_ARAM_REFRESH                (DSP_REG_BASE + 0x1A)           
#define         DSP_ARAM_DMA_MEMADDR_H          (DSP_REG_BASE + 0x20)           
#define         DSP_ARAM_DMA_MEMADDR_L          (DSP_REG_BASE + 0x22)           
#define         DSP_ARAM_DMA_ARAMADDR_H         (DSP_REG_BASE + 0x24)           
#define         DSP_ARAM_DMA_ARAMADDR_L         (DSP_REG_BASE + 0x26)           
#define         DSP_ARAM_DMA_SIZE_H             (DSP_REG_BASE + 0x28)           
#define         DSP_ARAM_DMA_SIZE_L             (DSP_REG_BASE + 0x2A)           
/* Audio buffer interface */
#define         DSP_DMA_START_H                 (DSP_REG_BASE + 0x30)           
#define         DSP_DMA_START_L                 (DSP_REG_BASE + 0x32)           
#define         DSP_DMA_SIZE                    (DSP_REG_BASE + 0x36)           
#define         DSP_DMA_LEFT                    (DSP_REG_BASE + 0x3A)           
#endif