HuC6270 (7up)

The 7up is a Video Display Controller. The PC-FX has two 7up chips. The PC-Engine used one 7up for it's video.

I/O Ports

	HuC6270-A	HuC6270-B
Register (W)	0x400	0x500
Status (R)	0x400	0x500
Data (R/W)	0x404	0x504

Register map

0x00	VRAM write address
0x01	VRAM read address
0x02	VRAM read/write
0x05	Control
0x06	Raster Compare
0x07	Background X-scroll
0x08	Background Y-scroll
0x09	Memory-access Width
0x0A	Horizontal Sync
0x0B	Horizontal Display
0x0C	Vertical Sync
0x0D	Vertical Display
0x0E	Vertical Display Position End
0x0F	DMA control
0x10	DMA transfer source
0x11	DMA destination address
0x12	DMA transfer length
0x13	Sprite Attribute Table Address

Register

0x00 VRAM write address (Half)

Address to write to in VRAM. Writes to 0x02 automatically increase this.

0x01 VRAM read address (Half)

Address to read from in VRAM. Reads from 0x02 automatically increase this.

0x02 VRAM read/write (Half)

When written, writes the data to the address in 0x00 then increases it.

When read, reads the data from the address in 0x01 then increases it.

0x05 Control (Half)

Set HuC6270 behavior

Bits	Description
0	Collision detection (write is masking)
1	Sprite overflow (write is masking)
2	Scanline match (write is masking)
3	Vblank (write is masking)
6	Display Sprite
7	Display BG
12 ~ 11	Auto-increase amounts	00 = +1
		01 = +32
		10 = +64
		11 = +128

0x06 Raster Compare (Half)

More information needed!

0x07 Background X-scroll (Half)

X scrolling. Latched during each scanline, preventing mid-scanline changes.

0x08 Background Y-scroll (Half)

Y scrolling. Latched during each scanline, preventing mid-scanline changes.

0x09 Memory-access Width (Half)

Configure the size of virtual background map.

Bits	Description
0 ~ 1	VRAM dot width
2 ~ 3	Sprite dot width
4 ~ 5	Virtual screen width	00 = 256 px (32 tile)
		01 = 512 px (64 tile)
		10 = 1024 px (128 tile)
		11 = 1024 px (128 tile)
6	Virtual screen height	0 = 256 px (32 tile)
6	Virtual screen height	1 = 512 px (64 tile)
7	CG Mode (determines which plane is used when VRAM dot width is 11)

0x0A Horizontal Sync (Half)

Horizontal sync width defines the width of the horizontal sync pulse in 8-pixel (character) units. The range is 1 to 32 characters. Horizontal display start defines the interval after the horizontal sync pulse to the start of the horizontal display period in character units. The range is 1 to 128 characters.

Bits	Description
0 ~ 4	Horizontal sync width
8 ~ 14	Horizontal display start - 1

0x0B Horizontal Display (Half)

Horizontal display width defines the width of the horizontal active display period in character units. The range is 1 to 128 characters. Horizontal display end defines the interval following HDE to the end of the scanline, at which poinst the Horizontal Sync state is entered and a horizontal sync pulse is generated. The range is 1 to 128 characters. It should be set to the remainder from the desired number of characters per scanline, minus HSW, HDS, and HDW.

Bits	Description
0 ~ 6	Horizontal display width - 1
8 ~ 14	Horizontal display end - 1

0x0C Vertical Sync (Half)

Vertical sync width defines the width of the vertical sync pulse in 8-pixel (character) units. The range is 1 to 32 characters. Vertical display start defines the interval after the vertical sync pulse to the start of the vertical display period in character units. The range is 1 to 128 characters.

Bits	Description
0 ~ 4	Vertical sync width
8 ~ 15	Vertical display start - 2

0x0C Vertical Display (Half)

Vertical display width defines the width of the vertical active display period in character units. The range is 1 to 512 characters.

Bits	Description
0 ~ 8	Vertical display width - 1

0x0E Vertical Display Position End (Half)

Vertical Display Position defines the interval following Vertical display to the end of the frame, at which point the Vertical Sync state is entered and a vertical sync pulse is generated. The range is 0 to 255 scanlines. It should be set to the remainder from the desired number of scanlines per frame, minus VSW, VDS, and VDW.

Bits	Description
0 ~ 7	Vertical display end

0x0F DMA control(Half)

Controls the DMA functionality.

Bits	Description
0	Interrupt at end of VRAM-SATB transfer. Checked at end of transfer.
1	Interrupt at end of VRAM-VRAM transfer. Checked at end of transfer.
2	Source address modification	0 = Increment
2	Source address modification	1 = Decrement
3	Destination address modification	0 = Increment
3	Destination address modification	1 = Decrement
4	DSR DMA (VRAM-SATB transfer repetition)

0x10 DMA transfer source (Half)

Source address for DMA transfers.

0x11 DMA destination address (Half)

Destination address for DMA transfers.

0x12 DMA transfer length (Half)

Length of DMA transfers. Setting this starts the DMA transfer.

0x13 Sprite attribute table address(Half)

Address of the Sprite Attribute Table

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