Handles processing BG transfers, SCSI transfers, ADPCM transfers, and RAINBOW transfers.
Main RAM cannot be accessed directly, transfer data to KRAM with the KRAM interface
Register (W) | 0x600 |
---|---|
Status (R) | 0x600 |
Status 2(R) | 0x602 |
Data (R/W) | 0x604 |
Data 2(R/W) | 0x606 |
Bits | Description |
---|---|
0 ~ 6 | Register selected |
9 | Busy |
10 | ADPCM buffer interrupt. Reading clears the interrupt. |
11 | HSync raster interrupt. "HuC6271 transfer control register's RINT bit (reg 0x40: bit1) reset and reset again to lead this state." |
12 | CD-ROM drive subcode interrupt. Reading clears this register's subcode or subcode register. |
13 | SCSI DMA end interrupt. Reading clears the SCSI DMA enable register. |
14 | SCSI block interrupt. SCSI bus reset occurs on a base phase mismatch. Reading clears SCSI reset interrupt register. |
16 ~ 23 | SCSI status. Just like register 0x05. |
24 ~ 31 | Sub-code |
Bits | READ | WRITE |
---|---|---|
0 ~ 7 | SCSI data | SCSI data |
Bits | READ | WRITE |
---|---|---|
0 | Bus | Bus |
1 | ATN (?) | ATN (?) |
2 | Select | Select |
4 | Acknowledge | Acknowledge |
7 | Reset | Reset |
Bits | READ | WRITE |
---|---|---|
0 | Sequential DMA | Sequential DMA |
1 | DMA | DMA |
Bits | READ | WRITE |
---|---|---|
0 | I/O | I/O |
1 | C/D | C/D |
2 | Misc | Misc |
Bits | READ | WRITE |
---|---|---|
0 | "Once the DMA has written to the DMA mode, this register from the output of the SCSI bus. DMA starts." | |
1 | Select | |
2 | I/O | |
3 | C/D | |
4 | Misc | |
5 | Request | |
6 | Busy | |
7 | Reset | |
16 ~ 23 | SCSI -> CPU data | CPU -> SCSI data |
Bits | READ | WRITE |
---|---|---|
0 ~ 7 | Data |
Bits | READ | WRITE |
---|---|---|
0 ~ 7 | Clear SCSI interrupt | Initiate SCSI DMA |
Bits | READ | WRITE |
---|---|---|
0 | Subcode | Subcode capture enable |
1 | Subcode interrupt enable | |
2 | ||
3 | ||
4 | ||
5 | ||
6 | ||
7 |
Bits | READ | WRITE |
---|---|---|
0 ~ 16 | DMA transfer address | DMA transfer address |
17 | A/B | A/B |
Bits | READ | WRITE |
---|---|---|
0 | 0 | |
1 ~ 17 | DMA transfer size | DMA transfer size |
Bits | READ | WRITE |
---|---|---|
0 | DMA ended | DMA enable |
1 | DMA end interrupt enable | |
7 | SCSI interface active level |
KRAM read address
Bits | Description |
---|---|
0 ~ 17 | Address |
18 ~ 27 | Increment address |
31 | Page |
KRAM write address
Bits | Description |
---|---|
0 ~ 17 | Address |
18 ~ 27 | Increment address |
31 | Page |
When written, writes the data to the address in 0x0C then increases it.
When read, reads the data from the address in 0x0D then increases it.
Setup the pages of KRAM for KING
Bits | Description |
---|---|
0 | KRAM page for SCSI |
8 | KRAM page for BG |
16 | KRAM page for RAINBOW |
24 | KRAM page for ADPCM |
BG mode setting
Bits | Description |
---|---|
0 ~ 3 | BG0 mode |
4 ~ 7 | BG1 mode |
8 ~ 11 | BG2 mode |
12 ~ 15 | BG3 mode |
Mode values are like so:
0000 | Unused |
---|---|
0001 | 4 palette |
0010 | 16 palette |
0011 | 256 palette |
0100 | 64k color |
0101 | 16M color |
1001 | 4 palette block mode |
1010 | 16 palette block mode |
1011 | 256 palette block mode |
BG prioritization
Bits | Description |
---|---|
0 ~ 2 | BG0 priority |
3 ~ 5 | BG1 priority |
6 ~ 8 | BG2 priority |
9 ~ 11 | BG3 priority |
12 | BG0 rotation enable (wtf NEC) |
Priority values are like so:
000 | Hidden |
---|---|
001 | Farthest back |
010 | Above back |
011 | Under first |
100 | Farthest forward |
101 110 111 | Prohibited |
Microprogram write address
Microprogram data to write. Autoincrements register 0x13.
Microprogram control.
Bits | Description |
---|---|
0 | Microprogram running |
Mode 0 is a single background area. Mode 1 is an endless background (looping?).
Bits | Description |
---|---|
0 | BG0's scroll mode |
1 | BG1's scroll mode |
2 | BG2's scroll mode |
3 | BG3's scroll mode |
BG0 BAT address. This is the address divided by 1024.
BG0 CG address. This is the address divided by 1024.
BG0sub BAT address. This is the address divided by 1024.
BG0sub CG address. This is the address divided by 1024.
BG1 BAT address. This is the address divided by 1024.
BG1 CG address. This is the address divided by 1024.
BG2 BAT address. This is the address divided by 1024.
BG2 CG address. This is the address divided by 1024.
BG3 BAT address. This is the address divided by 1024.
BG3 CG address. This is the address divided by 1024.
Specify BG0 size
Bits | Description |
---|---|
0 ~ 3 | Height |
4 ~ 7 | Width |
8 ~ 11 | Sub Height |
12 ~ 15 | Sub Width |
Size values are like so:
Bits | Description |
---|---|
0011 | 8 px |
0100 | 16 px |
0101 | 32 px |
0110 | 64 px |
0111 | 128 px |
1000 | 256 px |
1001 | 512 px |
1010 | 1024 px (only valid for BG0) |
Specify BG1 Size. Same settings as 0x2C, except no sub size.
Specify BG2 Size. Same settings as 0x2C, except no sub size.
Specify BG3 Size. Same settings as 0x2C, except no sub size.
The X coordinate of the upper-left corner of BG0.
The Y coordinate of the upper-left corner of BG0.
The X coordinate of the upper-left corner of BG1.
The Y coordinate of the upper-left corner of BG1.
The X coordinate of the upper-left corner of BG2.
The Y coordinate of the upper-left corner of BG2.
The X coordinate of the upper-left corner of BG3.
The Y coordinate of the upper-left corner of BG3.
Value is calculated like this, where a is the X zoom factor, and r is counter-clockwise rotation angle.
n = (1/a)*cos(r)
The value (n) is stored in an 8.8 fixed point format.
Value is calculated like this, where b is the Y zoom factor, and r is counter-clockwise rotation angle.
n = -(1/b)*sin(r)
The value (n) is stored in an 8.8 fixed point format.
Value is calculated like this, where a is the X zoom factor, and r is counter-clockwise rotation angle.
n = (1/a)*sin(r)
The value (n) is stored in an 8.8 fixed point format.
Value is calculated like this, where b is the Y zoom factor, and r is counter-clockwise rotation angle.
n = (1/b)*cos(r)
The value (n) is stored in an 8.8 fixed point format.
BG affine rotation center's X coordinate. Coordinate is relative to the center.
BG affine rotation center's Y coordinate. Coordinate is relative to the center.
Bits | Description |
---|---|
0 | Enable RAINBOW transfer |
1 | Interrupt on raster (specified by register 0x44) hit |
Address of KRAM to transfer data to RAINBOW.
Start RAINBOW transfer at this raster count (0 ~ 261).
Specifies the number of blocks of data RAINBOW transfers (1 block == 16 dots?) (0 ~ 31).
When the raster reaches this count, and if the interrupt bit in 0x40 is enabled, an interrupt is fired.
Bits | Description | |
---|---|---|
0 | Channel 0 play | |
1 | Channel 1 play | |
2 ~ 3 | Sampling rate | 00 = 31.47kHz |
01 = 15.73kHz | ||
10 = 7.87kHz | ||
11 = 3.93kHz |
When in ring buffer mode, the buffer contents are looped. Sequential mode uses streaming (I think?)
Bits | Description | |
---|---|---|
0 | Buffer Mode | 0 = Sequential |
1 = Ring | ||
1 | End interrupt | 0 = Disabled |
1 = Allow | ||
2 | Intermediate interrupt | 0 = Disabled |
1 = Allow |
Just like 0x51 but for channel 1.
Reading contents of this register clears the flags.
Interrupt is level-triggered, and must be cleared in the handler to prevent an infinite loop.
Bits | Description |
---|---|
0 | Channel 0 end interrupt |
1 | Channel 0 intermediate interrupt |
2 | Channel 1 end interrupt |
3 | Channel 1 intermediate interrupt |
Starting address, divided by 256.
End address, no division. If in ring buffer mode, start address is reloaded when this is hit. If in sequential mode, playing is stopped and the play bit in register 0x50 is reset.
Intermediate address, divided by 64. Used only if the intermediate interrupt bit in the channel's control is enabled.
Same contents as 0x58 for channel 1
Same contents as 0x59 for channel 1
Same contents as 0x5A for channel 1
KING's BG is generated by a microprogram. The microprogram is a program in KRAM that describes how to output KING backgrounds.
The microprogram is 16 half words long. Addresses 0 ~ 7 are the A bank address (?). Addresses 8 ~ 15 is the B bank address (?).
Bits | Description | |
---|---|---|
0 ~ 2 | Offset Offset of the data to access. If bit5 is set, this will always be 0. | |
3 ~ 4 | Data access types | 00 = CG data is accessed |
01 = BAT data associated to that CG data is accessed | ||
10 = BAT data is accessed | ||
11 = ??? | ||
5 | Rotation flag This bit is 1 when you do rotation. | |
6 ~ 7 | BG surface number Which BG will be operated upon. | |
8 | NOP flag When this bit is 1, the opcode will still be parsed, but nothing will occur. |
It is not possible to describe a microprogram that operates across banks.
16M color screen if it contains the rotation process can be done.
Non-rotating plane data width per 1dot 16bit or less. For example, 64k color screen and create a two-sided, three sides to create a color screen 256.
BG0 cannot be rotated.
Code | Operation |
---|---|
0000 | +0 from CG is accessed |
0001 | +1 from CG is accessed |
0002 | +2 from CG is accessed |
0003 | +3 from CG is accessed |
0004 | +4 from CG is accessed |
0005 | +5 from CG is accessed |
0006 | +6 from CG is accessed |
0007 | +7 from CG is accessed |
Code | Operation |
---|---|
0000 | +0 from CG is accessed |
0001 | +1 from CG is accessed |
0002 | +2 from CG is accessed |
0003 | +3 from CG is accessed |
Code | Operation |
---|---|
0000 | +0 from CG is accessed |
0001 | +1 from CG is accessed |
Code | Operation |
---|---|
0000 | +0 from CG is accessed |
Code | Operation |
---|---|
0010 | +0 from BAT read |
0100 | NOP |
0008 | +0 from BAT CG is accessed |
0009 | +1 from BAT CG is accessed |
000A | +2 from BAT CG is accessed |
000B | +3 from BAT CG is accessed |
Code | Operation |
---|---|
0010 | +0 from BAT read |
0100 | NOP |
0008 | +0 from BAT CG is accessed |
0009 | +1 from BAT CG is accessed |
Code | Operation |
---|---|
0010 | +0 from BAT read |
0100 | NOP |
0008 | +0 from BAT CG is accessed |
Code | Operation |
---|---|
0020 | Process rotation |
0020 | Process rotation |
0020 | Process rotation |
0020 | Process rotation |
0020 | Process rotation |
0020 | Process rotation |
0020 | Process rotation |
0020 | Process rotation |