bootmii_ppc.h File Reference

#include <types.h>
#include <broadway/hollywood.h>

Defines
#define	SPR_XER ( 1)
#define	SPR_LR ( 8)
#define	SPR_CTR ( 9)
#define	SPR_DSISR ( 18)
#define	SPR_DAR ( 19)
#define	SPR_DEC ( 22)
#define	SPR_SDR1 ( 25)
#define	SPR_SRR0 ( 26)
#define	SPR_SRR1 ( 27)
#define	SPR_SPRG0 ( 272)
#define	SPR_SPRG1 ( 273)
#define	SPR_SPRG2 ( 274)
#define	SPR_SPRG3 ( 275)
#define	SPR_EAR ( 282)
#define	SPR_PVR ( 287)
#define	SPR_IBAT0U ( 528)
#define	SPR_IBAT0L ( 529)
#define	SPR_IBAT1U ( 530)
#define	SPR_IBAT1L ( 531)
#define	SPR_IBAT2U ( 532)
#define	SPR_IBAT2L ( 533)
#define	SPR_IBAT3U ( 534)
#define	SPR_IBAT3L ( 535)
#define	SPR_DBAT0U ( 536)
#define	SPR_DBAT0L ( 537)
#define	SPR_DBAT1U ( 538)
#define	SPR_DBAT1L ( 539)
#define	SPR_DBAT2U ( 540)
#define	SPR_DBAT2L ( 541)
#define	SPR_DBAT3U ( 542)
#define	SPR_DBAT3L ( 543)
#define	SPR_GQR0 ( 912)
#define	SPR_GQR1 ( 913)
#define	SPR_GQR2 ( 914)
#define	SPR_GQR3 ( 915)
#define	SPR_GQR4 ( 916)
#define	SPR_GQR5 ( 917)
#define	SPR_GQR6 ( 918)
#define	SPR_GQR7 ( 919)
#define	SPR_HID2 ( 920)
#define	SPR_WPAR ( 921)
#define	SPR_DMA_U ( 922)
#define	SPR_DMA_L ( 923)
#define	SPR_UMMCR0 ( 936)
#define	SPR_UPMC1 ( 937)
#define	SPR_UPMC2 ( 938)
#define	SPR_USIA ( 939)
#define	SPR_UMMCR1 ( 940)
#define	SPR_UPMC3 ( 941)
#define	SPR_UPMC4 ( 942)
#define	SPR_USDA ( 943)
#define	SPR_MMCR0 ( 952)
#define	SPR_PMC1 ( 953)
#define	SPR_PMC2 ( 954)
#define	SPR_SIA ( 955)
#define	SPR_MMCR1 ( 956)
#define	SPR_PMC3 ( 957)
#define	SPR_PMC4 ( 958)
#define	SPR_SDA ( 959)
#define	SPR_HID0 (1008)
#define	SPR_HID1 (1009)
#define	SPR_IABR (1010)
#define	SPR_HID4 (1011)
#define	SPR_DABR (1013)
#define	SPR_L2CR (1017)
#define	SPR_ICTC (1019)
#define	SPR_THRM1 (1020)
#define	SPR_THRM2 (1021)
#define	SPR_THRM3 (1022)
#define	MEM2_BSS __attribute__ ((section (".bss.mem2")))
#define	MEM2_DATA __attribute__ ((section (".data.mem2")))
#define	MEM2_RODATA __attribute__ ((section (".rodata.mem2")))
#define	ALIGNED(x) __attribute__ ((aligned(x)))
#define	STACK_ALIGN(type, name, cnt, alignment)
	Creates an array on the stack.
#define	VIRT_TO_PHYS(x) ((u32)(x) & 0x3FFFFFFF)
#define	PHYS_TO_VIRT(x) ((u32)(x) \| 0x80000000)
#define	PHYS_TO_VIRT_NOCACHE(x) ((u32)(x) \| 0xC0000000)
#define	usleep(n) udelay(n)
#define	mftb() getticks()
#define	mtspr(n, x) asm("mtspr %1,%0" : : "r"(x), "i"(n))
	Moves a value into an SPR.
#define	mfspr(n)
	Gets the value of an SPR.
#define	reboot() write32(HW_RESETS, 0)
#define	hollywood_version() ((read32(HW_VERSION) >> 4) & 0xF)
#define	hollywood_revision() ((read32(HW_VERSION) >> 0) & 0xF)
Typedefs
typedef void(*	except_handler )(int exception)
	Exception handler type.
Functions
void	sync_before_read (void *p, u32 len)
	Invalidates the cache for the data.
void	flush_after_write (void *p, u32 len)
	Flushes the cache for the data.
void	sync_after_write (const void *p, u32 len)
	Stores the cache for the data.
void	sync_before_exec (const void *p, u32 len)
	Stores the cache for the data and invalidates the instructions.
void	ppcsync (void)
	Synchronizes the data and instruction caches.
void	udelay (u32 us)
	Delay with microsecond granularity.
u64	getticks ()
	Get processor ticks since power-on.
void	tickdelay (u64 ticks)
	Delay with processor tick granularity.
void	exception_init (void)
	Initializes exceptions.
Variables
volatile except_handler	exception_handler_table [0x10]

Detailed Description

All the SPRs for Broadway, and several PowerPC specific functions.

Define Documentation

#define hollywood_revision ( ) ((read32(HW_VERSION) >> 0) & 0xF)

Get the revision of the Hollywood

#define hollywood_version ( ) ((read32(HW_VERSION) >> 4) & 0xF)

Get the version of the Hollywood

#define MEM2_BSS __attribute__ ((section (".bss.mem2")))

Puts some data into the MEM2 .bss section

#define MEM2_DATA __attribute__ ((section (".data.mem2")))

Puts some data into the MEM2 .data section

#define MEM2_RODATA __attribute__ ((section (".rodata.mem2")))

Puts some data into the MEM2 .rodata section

#define mfspr ( n )

Value:

({ \
        u32 x; asm volatile("mfspr %0,%1" : "=r"(x) : "i"(n)); x; \
})

Gets the value of an SPR.

Parameters:

n

the SPR.

Returns:: The value of the SPR.

See also:: mfspr()

#define mftb ( ) getticks()

Renaming for processor terms

#define mtspr	(	n,
		x		)	asm("mtspr %1,%0" : : "r"(x), "i"(n))

Moves a value into an SPR.

Parameters:

	n	the SPR.
	x	the value to be put into the SPR.

See also:: mfspr()

#define PHYS_TO_VIRT ( x ) ((u32)(x) | 0x80000000)

Converts physical addresses to cached virtual

#define PHYS_TO_VIRT_NOCACHE ( x ) ((u32)(x) | 0xC0000000)

Converts physical addresses to uncached virtual

#define reboot ( ) write32(HW_RESETS, 0)

Reboot the system

#define SPR_CTR ( 9)

Count Register

#define SPR_DABR (1013)

Data Address Breakpoint Register

#define SPR_DAR ( 19)

Data Address Register

#define SPR_DBAT0L ( 537)

Data Block-address Translation Lower Register 0

#define SPR_DBAT0U ( 536)

Data Block-address Translation Upper Register 0

#define SPR_DBAT1L ( 539)

Data Block-address Translation Lower Register 1

#define SPR_DBAT1U ( 538)

Data Block-address Translation Upper Register 1

#define SPR_DBAT2L ( 541)

Data Block-address Translation Lower Register 2

#define SPR_DBAT2U ( 540)

Data Block-address Translation Upper Register 2

#define SPR_DBAT3L ( 543)

Data Block-address Translation Lower Register 3

#define SPR_DBAT3U ( 542)

Data Block-address Translation Upper Register 3

#define SPR_DEC ( 22)

Decrementer Register

#define SPR_DMA_L ( 923)

Direct Memory Access Lower Register

#define SPR_DMA_U ( 922)

Direct Memory Access Upper Register

#define SPR_DSISR ( 18)

DSI Exception Cause Register

#define SPR_EAR ( 282)

External Access Register

#define SPR_GQR0 ( 912)

Graphics Quantization Register 0

#define SPR_GQR1 ( 913)

Graphics Quantization Register 1

#define SPR_GQR2 ( 914)

Graphics Quantization Register 2

#define SPR_GQR3 ( 915)

Graphics Quantization Register 3

#define SPR_GQR4 ( 916)

Graphics Quantization Register 4

#define SPR_GQR5 ( 917)

Graphics Quantization Register 5

#define SPR_GQR6 ( 918)

Graphics Quantization Register 6

#define SPR_GQR7 ( 919)

Graphics Quantization Register 7

#define SPR_HID0 (1008)

Hardware Implementation-Dependant Register 0

#define SPR_HID1 (1009)

Hardware Implementation-Dependant Register 1

#define SPR_HID2 ( 920)

Hardware Implementation-Dependant Register 2

#define SPR_HID4 (1011)

Hardware Implementation-Dependant Register 4

#define SPR_IABR (1010)

Instruction Address Breakpoint Register

#define SPR_IBAT0L ( 529)

Instruction Block-address Translation Lower Register 0

#define SPR_IBAT0U ( 528)

Instruction Block-address Translation Upper Register 0

#define SPR_IBAT1L ( 531)

Instruction Block-address Translation Lower Register 1

#define SPR_IBAT1U ( 530)

Instruction Block-address Translation Upper Register 1

#define SPR_IBAT2L ( 533)

Instruction Block-address Translation Lower Register 2

#define SPR_IBAT2U ( 532)

Instruction Block-address Translation Upper Register 2

#define SPR_IBAT3L ( 535)

Instruction Block-address Translation Lower Register 3

#define SPR_IBAT3U ( 534)

Instruction Block-address Translation Upper Register 3

#define SPR_ICTC (1019)

Instruction Cache Throttling Control Register

#define SPR_L2CR (1017)

L2 Cache Control Register

#define SPR_LR ( 8)

Link Register

#define SPR_MMCR0 ( 952)

Monitor Mode Control Register 0

#define SPR_MMCR1 ( 956)

Monitor Mode Control Register 1

#define SPR_PMC1 ( 953)

Performance Monitor Count Register 1

#define SPR_PMC2 ( 954)

Performance Monitor Count Register 2

#define SPR_PMC3 ( 957)

Performance Monitor Count Register 3

#define SPR_PMC4 ( 958)

Performance Monitor Count Register 4

#define SPR_PVR ( 287)

Processor Version Register

#define SPR_SDA ( 959)

Sampled Data Address Register

#define SPR_SDR1 ( 25)

Page Table base address

#define SPR_SIA ( 955)

Sampled Instruction Address Register

#define SPR_SPRG0 ( 272)

OS reserved

#define SPR_SPRG1 ( 273)

OS reserved

#define SPR_SPRG2 ( 274)

OS reserved

#define SPR_SPRG3 ( 275)

OS reserved

#define SPR_SRR0 ( 26)

Save/Restore Register 0

#define SPR_SRR1 ( 27)

Save/Restore Register 1

#define SPR_THRM1 (1020)

Thermal Management Register 1

#define SPR_THRM2 (1021)

Thermal Management Register 2

#define SPR_THRM3 (1022)

Thermal Management Register 3

#define SPR_UMMCR0 ( 936)

User Monitor Mode Control Register 0

#define SPR_UMMCR1 ( 940)

User Monitor Mode Control Register 0

#define SPR_UPMC1 ( 937)

User Performance Monitor Count Register 1

#define SPR_UPMC2 ( 938)

User Performance Monitor Count Register 2

#define SPR_UPMC3 ( 941)

User Performance Monitor Count Register 3

#define SPR_UPMC4 ( 942)

User Performance Monitor Count Register 4

#define SPR_USDA ( 943)

User Sampled Data Address Register

#define SPR_USIA ( 939)

User Sampled Instruction Address Register

#define SPR_WPAR ( 921)

Write Pipe Address Register

#define SPR_XER ( 1)

Integer Exception Register

#define STACK_ALIGN	(	type,
		name,
		cnt,
		alignment	)

Value:

u8 _al__##name[((sizeof(type)*(cnt)) + (alignment) + \
        (((sizeof(type)*(cnt))%(alignment)) > 0 ? ((alignment) - \
        ((sizeof(type)*(cnt))%(alignment))) : 0))]; \
        type *name = (type*)(((u32)(_al__##name)) + ((alignment) - (( \
        (u32)(_al__##name))&((alignment)-1))))

Creates an array on the stack.

Uhh...

Parameters:

	type	the type of array to be created.
	name	the name of the array to be created.
	cnt	how many "type"s to allocate.
	alignment	how many bytes to align the array to.

#define usleep ( n ) udelay(n)

Renaming for compatibility

#define VIRT_TO_PHYS ( x ) ((u32)(x) & 0x3FFFFFFF)

Converts virtual addresses to physical

Function Documentation

void flush_after_write	(	void *	p,
		u32	len
	)

Flushes the cache for the data.

Parameters:

	p	the start of the memory that was written.
	len	how far the cache needs to be flushed.

u64 getticks ( )

Get processor ticks since power-on.

Returns:: How many processor ticks have elapsed since power-on.

void sync_after_write	(	const void *	p,
		u32	len
	)

Stores the cache for the data.

Parameters:

	p	the start of the memory that was written.
	len	how far the cache needs to be stored.

void sync_before_exec	(	const void *	p,
		u32	len
	)

Stores the cache for the data and invalidates the instructions.

Parameters:

	p	the start of the memory that is to be executed.
	len	how far the cache needs to be stored and invalidated.

void sync_before_read	(	void *	p,
		u32	len
	)

Invalidates the cache for the data.

Parameters:

	p	the start of the memory to be read.
	len	how far the cache needs to be invalidated.

void tickdelay ( u64 ticks )

Delay with processor tick granularity.

Parameters:

ticks

how many processor ticks to wait.

void udelay ( u32 us )

Delay with microsecond granularity.

Parameters:

us

how many microseconds to delay.

Variable Documentation

volatile except_handler exception_handler_table[0x10]

Exception handler table

bootmii_ppc.h File Reference

Defines

Typedefs

Functions

Variables

Detailed Description

Define Documentation

Function Documentation

Variable Documentation